A clock-fault tolerant architecture and circuit for reliable nanoelectronics system

Due to discrepancies in manufacturing process and the probabilistic nature of quantum mechanical phenomenon, nanoelectronic devices cannot be made as reliable as current microelectronic devices. As a result, fault-tolerant architectures are a prerequisite to building reliable electronic systems from these unreliable nanoelectronic devices. One important design aspect of nanoelectronic architecture that demands attentive consideration is clock generation and distribution. Various defects and interference such as doping discrepancies, supply noise and cross-talks could lead to clock irregularity and malformed clock signals, thus resulting in faulty operations of sequential circuits. Generally, these errors are not readily amenable to efficient correction using error-correcting codes known to date. In this paper, we propose a novel fault-tolerant architecture for a parallel computation structure. The fault-tolerance capabilities built into this architecture allow for effective remedy against the deleterious effects of random clock abnormality and reduce the probability of computational errors. Central to the operation of the proposed fault-tolerant architecture is a novel clock-fault detection circuitry. In order to illustrate the fault- tolerance capability rendered by the detection circuitry, an error probability analysis is performed. Finally, a prototype CMOS design of this proposed circuit that consists of only 28 transistors and 2 capacitors is presented. Our simulation shows that with only a two-fold increase in hardware counts, the proposed architecture can gain significant fault-tolerance capability.