A study of IR-drop noise issues in 3D ICs with through-silicon-vias

With the extensive research on through-silicon-via (TSV) and die-stacking technology from both academia and industry, mainstream production of 3D ICs is expected in a near future. However, power delivery is believed to be one of the most challenging problems in 3D ICs. A main objective of the 3D power/ground (P/G) network optimization is to minimize the usage of P/G TSVs while satisfying power supply noise constraint. P/G TSVs consume a considerable amount of routing resources unless designed carefully. In this work, we first investigate the impact of P/G TSVs on the power supply noise as well as 3D IC layouts. We perform sign-off static IR-drop analysis on GDSII layouts of 2D and 3D IC designs using commercial-grade tools. We also explore the impact of 3D P/G network topology on IR-drop by varying P/G TSV pitch. Next, we propose a non-regular P/G TSV placement algorithm to further reduce the number of P/G TSVs used while satisfying the given IR-drop noise requirement. Compared with the conventional regular structure, our non-regular P/G TSV placement algorithm reduces the P/G TSV count, wirelength, and footprint area by 59.3%, 3.4%, and 3.5% on average, respectively.