Fully integrated active filter design forultra low frequency application

Author

Darweesh, Hala Y. ; Khalaf, Yaser A. ; Farag, Fathi A.

Author_Institution

Zagazig Univ., Zagazig

fYear

2007

fDate

2-5 Sept. 2007

Firstpage

225

Lastpage

228

Abstract

This paper presents a new active capacitance multiplier circuit, by which it is possible to obtain higher capacitance values. The capacitance multiplier is based on cascaded current multiplier cells (CMC). The proposed circuit is preferred for low power low voltage applications since it is based on CMOS inverters and op-amps. The capacitance multiplier is employed in the design of a first order LPF with a cutoff frequency as low as 135 Hz using an on-chip capacitor of 1 pF only. The circuit is simulated in CMOS 0.13 mum process. Simulation results show close agreement with the analytical calculations.

Keywords

CMOS integrated circuits; active filters; capacitance; cascade networks; low-power electronics; multiplying circuits; CMOS inverter; active capacitance multiplier circuit; cascaded current multiplier cells; fully integrated active filter design; op-amps; size 0.13 mum; Active filters; Analytical models; CMOS process; Capacitance; Capacitors; Circuit simulation; Cutoff frequency; Inverters; Low voltage; Operational amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on

Conference_Location

Rabat

Print_ISBN

978-1-4244-1277-8

Electronic_ISBN

978-1-4244-1278-5

Type

conf

DOI

10.1109/DTIS.2007.4449525

Filename

4449525