DocumentCode
2970678
Title
Implementation of short-time classical HC stresses for in-line reliability control of sub-0.5 μm nMOSFETs
Author
Gonella, R.
Author_Institution
Central R&D Labs., STMicroelectron., Crolles, France
fYear
2000
fDate
2000
Firstpage
149
Lastpage
152
Abstract
The purpose of this paper is to show that in advanced sub-0.5 μm technologies, short-time classical hot-carrier (HC) stress tests are suitable for a predictive in-line monitoring. The ability of such tests in detecting maverick lots and the comparison with the performances of an already proposed fast method, lead to consider this approach as very attractive for wafer-level reliability control (WLRC) purposes
Keywords
MOSFET; hot carriers; life testing; semiconductor device reliability; semiconductor device testing; 0.5 micron; in-line reliability control; nMOSFETs; predictive in-line monitoring; short-time classical HC stresses; wafer-level reliability control; Breakdown voltage; Centralized control; Degradation; Integrated circuit reliability; MOSFET circuits; Monitoring; Performance evaluation; Stress control; Testing; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2000 IEEE International
Conference_Location
Lake Tahoe, CA
Print_ISBN
0-7803-6392-2
Type
conf
DOI
10.1109/IRWS.2000.911925
Filename
911925
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