Design and Implement of MVB BUS Controller Based FPGA

Author

Zuo, Lixia ; Ding, Qingfeng ; Tang, Yunbao

Author_Institution

Electr. Eng. Depts., East China Jiaotong Univ. Nanchang, Nanchang, China

fYear

2010

fDate

13-14 Oct. 2010

Firstpage

232

Lastpage

235

Abstract

This paper introduces the TCN MVB (Multifunction Vehicle Bus) communication mechanism and characteristics. On this basis, a method of VHDL language is designed for the core part of MVBC (MVB bus controller), such as the Manchester encoding and decoding, CRC check functions, etc. Among them, the bus´s CRC checksum data is formed with a double check of the 8-bit check sequence, including the 7 CRC checksum and an even parity bit. As different frame formats of MVB bus, serial CRC algorithm is choosed. Eventually, the right simulation waveforms of the cores of MVBC is obtained and realized on FPGA hardware.

Keywords

decoding; encoding; field buses; field programmable gate arrays; hardware description languages; railway communication; transport control; CRC check functions; MVB bus controller based FPGA; Manchester encoding; VHDL language; check sequence; decoding; double check; even parity bit; multifunction vehicle bus communication mechanism; train communication network; word length 8 bit; Access control; Codecs; Decoding; Encoding; Field programmable gate arrays; Registers; Synchronization; CRC; FPGA; MVBC; Manchester; decoding; encoding;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Intelligence Information Security (ICCIIS), 2010 International Conference on

Conference_Location

Nanning

Print_ISBN

978-1-4244-8649-6

Electronic_ISBN

978-0-7695-4260-7

Type

conf

DOI

10.1109/ICCIIS.2010.36

Filename

5629234