DocumentCode :
2972003
Title :
Queuing Analysis for Reconfigurable Computing
Author :
Hassanli, Kourosh ; Mahani, Ali Khayatzadeh ; Shahhoseini, Hadishahriar ; Teimoury, Ebrahim
Author_Institution :
Jahrom Branch, Dept. of Telecommun. Eng., Islamic Azad Univ., Jahrom
fYear :
2008
fDate :
2-3 Aug. 2008
Firstpage :
284
Lastpage :
288
Abstract :
Evaluation of reconfigurable hardware is an important part of designing the computer systems. In this paper two previously used recourse management mode for reconfigurable system, restricted and split mode described, a third mode (which is called merge mode) is introduced and all modes are analyzed. To analysis the queuing model are applied. The M/M/1/k queue is used. FPGA utilization and speedup are determined as two main metrics for system performance evaluation. To compare the modes with each others under different circumstances the metrics is found and plotted. The performance curve show proposed mode is act better than two previous modes, and has resource management. It is more effective when the larger task must be run on the system.
Keywords :
field programmable gate arrays; performance evaluation; queueing theory; reconfigurable architectures; FPGA utilization; M/M/l/k queue; queuing analysis; reconfigurable computing; recourse management mode; system performance evaluation; Analytical models; Application specific integrated circuits; Design engineering; Field programmable gate arrays; Hardware; Intelligent transportation systems; Power engineering and energy; Processor scheduling; Queueing analysis; Telecommunication computing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Electronics and Intelligent Transportation System, 2008. PEITS '08. Workshop on
Conference_Location :
Guangzhou
Print_ISBN :
978-0-7695-3342-1
Type :
conf
DOI :
10.1109/PEITS.2008.125
Filename :
4634861
Link To Document :
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