Low power CMOS circuit for spike detection

We present a compact CMOS circuit implementation for detection of neural spikes from noisy background. The circuit occupies 105 μm × 105 μm. Due to its small size, the circuit is well suited for spike detection in large format, high density microelectrode arrays where the chip area is the primary limiting constraint. The design consists of an amplifier and a differentiator to improve spike detection when the signal to noise ratio (SNR) is low. The circuit design parameters provide a circuit frequency response that rejects signals outside the neural data bandwidth (250 Hz to 2.5 kHz). Most of the transistors operate in subthreshold region and it consumes approx. 300 μW of power. We tested our design by simulations using synthetic data and actual neural recordings from the auditory cortex of ferrets. ROC results show derivative approach performed better than no processing in presence of noise.