• DocumentCode
    2973015
  • Title

    Coping with RC(L) interconnect design headaches

  • Author

    Pileggi, L.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    1995
  • fDate
    5-9 Nov. 1995
  • Firstpage
    246
  • Lastpage
    253
  • Abstract
    Physical interconnect effects have a dominant impact on today´s deep submicron IC designs. In this tutorial paper we will describe the technology trends which have brought about this interconnect dominance, then consider some of the modeling and analysis approximations available for both pre- and post-layout interconnect design. This coverage will not be an exhaustive summary, but one that is primarily focused on moment-based analysis techniques, from the Elmore delay, to the more recent advances in moment-matching approximations, and the corresponding nonlinear driver/load interfaces. Future modeling, analysis, and design challenges will be considered throughout this paper.
  • Keywords
    circuit CAD; integrated circuit design; integrated circuit interconnections; technological forecasting; Elmore delay; interconnect; interconnect design; moment-based analysis; moment-matching approximations; submicron IC designs; CMOS technology; Conductors; Contracts; Delay; Metallization; Paper technology; Semiconductor device modeling; Transistors; Wires; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA, USA
  • ISSN
    1092-3152
  • Print_ISBN
    0-8186-8200-0
  • Type

    conf

  • DOI
    10.1109/ICCAD.1995.480019
  • Filename
    480019