DocumentCode :
2973167
Title :
Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs
Author :
Unnikrishnan, Divya ; Virupaksha, Sandesh Gubbi ; Krishnan, Lakshmi ; Gao, Lei ; Tessier, Russell
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA
fYear :
2013
fDate :
9-11 Dec. 2013
Firstpage :
66
Lastpage :
73
Abstract :
Iterative algorithms represent a pervasive class of data mining, web search and scientific computing applications. In iterative algorithms, a final result is derived by performing repetitive computations on an input data set. Existing techniques to parallelize such algorithms typically use software frameworks such as MapReduce and Hadoop to distribute data for an iteration across multiple CPU-based workstations in a cluster and collect per-iteration results. These platforms are marked by the need to synchronize data computations at iteration boundaries, impeding system performance. In this paper, we demonstrate that FPGAs in distributed computing systems can serve a vital role in breaking this synchronization barrier with the help of asynchronous accumulative updates. These updates allow for the accumulation of intermediate results for numerous data points without the need for iteration-based barriers allowing individual nodes in a cluster to independently make progress towards the final outcome. Computation is dynamically prioritized to accelerate algorithm convergence. A general-class of iterative algorithms have been implemented on a cluster of four FPGAs. A speedup of 7× is achieved over an implementation of asynchronous accumulative updates on a general-purpose CPU. The system offers up to 154× speedup versus a standard Hadoop-based CPU-workstation. Improved performance is achieved by clusters of FPGAs.
Keywords :
distributed processing; field programmable gate arrays; iterative methods; synchronisation; algorithm convergence; distributed computing systems; iteration-based barriers; standard Hadoop-based CPU-workstation; Computational modeling; Field programmable gate arrays; Hardware; Iterative methods; Random access memory; Synchronization; Web pages;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2013 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-2199-7
Type :
conf
DOI :
10.1109/FPT.2013.6718332
Filename :
6718332
Link To Document :
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