Scalable hardware earliest-deadline-first scheduler for ATM switching networks

A fast, scalable hardware earliest deadline first (EDF) link scheduler for ATM switching network is developed. This EDF scheduler is a fast hardware solution suitable for real time scheduler on nodes in ATM switching networks up to 2.5 Gbps switching speed (scheduling within 0.17 /spl mu/s), capable of performing simultaneous input and output operations within two clock cycles (mostly in one clock cycle). The designed hardware is efficient since the architecture employs the minimum size EDF priority queue, combined with variable size FIFO queues for channels implemented with a two port memory buffer. Early traffic can be simply checked and delayed. Also, it is scalable with respect to the number of channels C and the total number of buffers N. Moreover, deadline folding technique eliminates the need to extend the deadline resolution. Simulation studies and layout design demonstrate the efficiency and utility of the proposed architecture.