Efficient use of large don´t cares in high-level and logic synthesis

This paper describes optimization techniques using don´t-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: (1) how to describe and extract don´t-care conditions from high-level descriptions; (2) how to pass don´t-care conditions from high-level to logic synthesis; and (3) how to optimize the logic using don´t-care conditions. Efficient techniques are given for these three problems which allow the use of large don´t-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization.