High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients

Performance and power consumption are two important aspects of reconfigurable finite impulse response (FIR) filters. In this paper, a new reconfigurable FIR architecture named SCSD FIR is proposed. This proposed architecture has been synthesized in 0.13 μm technology with a precision of 16 bits. Design example shows that FIR with 551 taps achieves 21.3% area reduction and 19.0% power reduction compared with the most efficient existing architecture of FIRs. It also achieves an improvement of 13.1% in speed. Furthermore, these advantages are expanded as the taps of filters are increasing.