Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation

Word-length optimisation techniques have traditionally been used to minimise the precision in a fixed hardware datapath subject to a given error tolerance. In this paper, we discuss how using word-length optimisation techniques to structure a hardware datapath can result in designs achieving the same functionality with even less silicon area. To demonstrate this, we revisit the addition reduction circuit and its use within matrix-vector multiplication. Our results show that given freedom over how to parallelise this circuit, for a fixed error and latency budget we can obtain mean silicon area savings of 58% a typical fixed-point design. We achieve this by creating a more numerically stable parallel architecture instead of replicating the initial design. Since freedom over datapath design is common for high-level synthesis tools, we hope this will inspire word-length optimisation techniques to be applied at the same time as making structural decisions within the design flow of these tools.