Title :
HITIBAS-A High-Throughput Input-Buffered ATM Switch
Author :
García-Haro, Joan ; Fan, Fai ; Jajszczyk, Andrzej
Author_Institution :
Dept. of Appl. Math. & Telematics, Polytech. Univ. of Catalonia, Barcelona, Spain
Abstract :
An economically feasible input-buffered ATM switch architecture with a low hardware complexity is described. Each input is provided with a completely shared memory pool that is logically divided into several FIFO queues, one for each output port. Head of line blocking is, therefore, avoided and a high throughput is achieved. The packet selection is accomplished in a modified cyclic order, in such a way that if a Banyan or an omega network is used, the entire system is internally nonblocking
Keywords :
asynchronous transfer mode; buffer storage; packet switching; queueing theory; shared memory systems; FIFO queues; input-buffered ATM switch; packet selection; shared memory pool; throughput; Asynchronous transfer mode; B-ISDN; Communication switching; Delay; Fabrics; Hardware; Packet switching; Switches; Throughput; Traffic control;
Conference_Titel :
Networks, 1993. International Conference on Information Engineering '93. 'Communications and Networks for the Year 2000', Proceedings of IEEE Singapore International Conference on
Print_ISBN :
0-7803-1445-X
DOI :
10.1109/SICON.1993.515786
