DocumentCode :
2974652
Title :
Statistically calculating reject limits at parametric test
Author :
Michelson, Diane K.
Author_Institution :
Harris Semicond., Findlay, OH, USA
fYear :
1997
fDate :
13-15 Oct 1997
Firstpage :
172
Lastpage :
177
Abstract :
Known Good Die (KGD) methodology is a process used in the manufacture of semiconductor chips which determines reject limits for parameters measured at sample probe. The philosophy of KGD is to set reject limits on all sample probe parameters at x¯±4 s, where x¯ is the sample average and s is the sample standard deviation, assuming a normal distribution on the parameter. When the distribution of measurements is normal, limits set at ±4 s correspond to a Cpk of 1.33. If the distribution of measurements is not normal, we examine using a generalized Cpk formula to find the KGD limits. KGD methods are also used to set limits at circuit probe and final test, after the chip has been packaged
Keywords :
integrated circuit manufacture; integrated circuit testing; statistical analysis; Known Good Die methodology; circuit probe; normal distribution; parametric testing; process capability index; reject limit; semiconductor chip manufacture; statistical analysis; Circuit testing; Fabrication; Gaussian distribution; Integrated circuit measurements; Integrated circuit packaging; Manufacturing processes; Probes; Semiconductor device manufacture; Semiconductor device measurement; Semiconductor device packaging;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1997., Twenty-First IEEE/CPMT International
Conference_Location :
Austin, TX
ISSN :
1089-8190
Print_ISBN :
0-7803-3929-0
Type :
conf
DOI :
10.1109/IEMT.1997.626895
Filename :
626895
Link To Document :
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