Architecture optimization of a finite impulse response filter using toggle-based power estimation

In this paper one way of reducing the power consumption and the area of a finite impulse response (FIR) filter is presented. Using a standard toggle-based power estimation method combined with gate-level simulations and circuit synthesis we showed that we can achieve a significant area and power reduction from the beginning by carefully selecting the right architecture and optimizing the VHDL code description of the module. The analysis was made based on the unity delay model and not on the physical extracted layout for an actual submicron technology (130 nm) but this method can be utilized successfully for other technologies.