Design and implementation of efficient CODECs for on-chip buses to reduce both crosstalk delay and power dissipation

With shrinking of Integrated Circuits feature sizes, the separation between the wires decreases which causes the coupling capacitance to increase, which in turn increases the crosstalk between the wires. The on-chip crosstalk causes, power consumption of interconnects and delay to increase. As the complexity of integrated circuits increase, the bus width increases, this causes the signal integrity issues. On-chip long wires that have large capacitance and coupling capacitance between wires are dominant in deep sub-micron process. In modern day CMOS circuit design, minimizing the power dissipation and the delay due to cross-talk in data propagation has been of much great interest to the research community. An important component of power consumption and delay due to crosstalk in processors is the transmission of data through high capacitance system-level buses. Crosstalk induced delay and power consumption have become a major determinant of the system performance. Reducing crosstalk can greatly boost the system performance. Bus encoding Schemes can achieve the same amount of bus delay improvement as passive shielding with a much lower area overhead. This paper provides a codec design and its experimental results.