A high speed protocol processor to boost gateway performance

Author

Hirata, Tetsuhiko ; Matsui, Susumu ; Yokoyama, Tatsuya ; Mizutani, Mika ; Terada, Matsuaki

Author_Institution

Hitachi Ltd., Kanagawa, Japan

fYear

1990

fDate

2-5 Dec 1990

Firstpage

1426

Abstract

The authors propose a high-speed protocol processor for gateways based on the following concept: normal data transfer is executed by special-purpose hardware and a general-purpose microprocessor handles abnormal data transfer and connection control. To analyze the quantitative effect of this proposal, a high-speed protocol processor which can execute OSI (open systems interconnection) layers two to four was manufactured, and its performance was measured. The protocol processing time for normal data transfer in the experimental system is 1/12 that of the conventional system on the transmission side and 1/7 that of the conventional system on the reception side. This result shows that application of the high-speed protocol processor in protocol-converting gateways is effective for improving performance

Keywords

computer interfaces; computer networks; open systems; protocols; OSI; abnormal data transfer; computer networks; connection control; gateway performance; high speed protocol processor; normal data transfer; protocol-converting gateways; Communication networks; Data communication; Hardware; IP networks; LAN interconnection; Laboratories; Microprocessors; Protocols; Standardization; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1990, and Exhibition. 'Communications: Connecting the Future', GLOBECOM '90., IEEE

Conference_Location

San Diego, CA

Print_ISBN

0-87942-632-2

Type

conf

DOI

10.1109/GLOCOM.1990.116728

Filename

116728