Partitioning transition relations efficiently and automatically

Author

Zhou, Z. ; Song, Xiaoyu ; Corella, F. ; Cerny, E. ; Langevin, M.

Author_Institution

Dept. d´´Inf. et de Recherche Oper., Montreal Univ., Que., Canada

fYear

1995

fDate

16-18 Mar 1995

Firstpage

106

Lastpage

111

Abstract

Multiway Decision Graphs (MDGs) have been recently proposed as an efficient representation of Extended Finite State Machines (EFSMs), suitable for automatic hardware verification of Register Transfer Level (RTL) designs. We report here on the results of our research into automatic partitioning of state transition relations described using MDGs. The objective is to achieve the maximum possible performance during an abstract implicit state enumeration procedure that is at the basis of our automatic verification method

Keywords

finite state machines; graph theory; logic CAD; logic partitioning; state estimation; abstract implicit state enumeration procedure; automatic partitioning; automatic verification method; extended finite state machines; multiway decision graphs; register transfer level designs; state transition relations; Automata; Boolean functions; Circuits; Concrete; Data structures; Hardware; Modular construction; Partitioning algorithms; Process design; Reachability analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Conference_Location

Buffalo, NY

ISSN

1066-1395

Print_ISBN

0-8186-7035-5

Type

conf

DOI

10.1109/GLSV.1995.516034

Filename

516034