Parallel hierarchical global routing for general cell layout

Author

Khanna, Sanjay ; Gao, Shaodi ; Thulasiraman, K.

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

fYear

1995

fDate

16-18 Mar 1995

Firstpage

212

Lastpage

215

Abstract

In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine and experiment results on different examples show relative speedup between 4 and 5 for 8 processors. The speedup is achieved without compromising the quality of the routing results

Keywords

VLSI; circuit layout CAD; integer programming; integrated circuit layout; network routing; parallel algorithms; general cell layout; hierarchical decomposition strategy; integer programming; network flow optimization; parallel hierarchical global routing; parallel processing; routing algorithm; shared-memory machine; Algorithm design and analysis; Circuits; Fabrication; Linear programming; Parallel algorithms; Parallel processing; Routing; Software tools; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1995. Proceedings., Fifth Great Lakes Symposium on

Conference_Location

Buffalo, NY

ISSN

1066-1395

Print_ISBN

0-8186-7035-5

Type

conf

DOI

10.1109/GLSV.1995.516055

Filename

516055