FPGA design of a real-time implementation of dynamic range compression for improving television picture

This paper presents efficient FPGA hardware architecture for the implementation of a digital video processing algorithm for improving picture quality when displayed on devices such as LCD and PDP panels. The algorithm performs dynamic range compression on the photographic quality input video and produces the output suitable for displaying on the panel. The algorithm is based on bilateral filter. Bilateral filter is a type of non-iterative smoothing filter that preserves edge information. The proposed architecture demonstrates a good compromise between filter performance and FPGA resource requirements. The architecture was prototyped in hardware using FPGA. The design and simulation was carried out using system-level approach.