A RAM-based generic packet switch with scheduling capability

A generic hardware solution is introduced for switching variable-length packets. The switch can be used in a multiprotocol environment including IP and ATM protocols. In this architecture the packets and/or cells are stored in a shared RAM memory as the main storage resource in the switch, and similar to RAM-based, shared-buffer ATM switch, for each packet a fixed-length minicell is given to a queue controller which provides queueing and scheduling. A bank of sequencer circuits can be used as the controller. We introduce a new version of the single-queue switch, as a compact controller to replace the bank of sequencers with a single sequencer, with the same speed and size. Fair queueing scheduling is implemented by the controller. Other schemes can also be implemented using the sequencer circuit, such as priority queueing. Plug-in modules handle the link and network (routing) protocols. Therefore, these modules can be easily changed or replaced. Multiple protocol modules are also possible in this way. High speed switching is possible in this architecture because the original packets and cells and also the minicells are handled by hardware. The hardware also provides a multicasting capability