Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count

A flash analog-to-digital converter (ADC) using multiplexers (MUXs) to reduce the number of preamplifiers and comparators is reported. A traditional N-bit flash ADC requires 2^N-1 preamplifiers and comparators while the proposed ADC only needs 2^(N-3)+2 preamplifiers and 2^(N-2)+1 comparators. For a 6-bit resolution, the proposed ADC requires a reduce number of preamplifiers and comparators by 84% and 73%, respectively, compare with those of the conventional flash ADC. The proposed 6-bit ADC consists of a reference ladder, a track-and-hold circuit, 10 preamplifiers, 17 comparators, a (2×1)-MUX, 8 (4×1)-MUXs and logic gates for encoder and registers. The proposed ADC is designed in a 1P6M 0.18-μm CMOS process with 1-V supply voltage and consumes 0.4-mW. At 50-MS/s, the proposed flash ADC has the effective number of bits of 5.46-bit and the figure of merit of 0.18 pJ/conversion-step.