DocumentCode :
2976670
Title :
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design
Author :
Shen, Zheng ; He, Hu ; Zhang, Yanjun ; Sun, Yihe
Author_Institution :
Tsinghua University, China
fYear :
2006
fDate :
Dec. 2006
Firstpage :
587
Lastpage :
592
Abstract :
This paper describes a novel video specific instruction set architecture for ASIP design. With SIMD (Single Instruction Multiple Data) instructions, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS ISA (Video Specific Instruction Set Architecture), other DSPs (digital signal processors) and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS ISA improves the processor¿s performance by approximate 5x on H.263 encoding, and VS ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.
Keywords :
Application specific processors; Computer architecture; Coprocessors; Digital signal processing; Digital signal processing chips; Encoding; Instruction sets; Registers; Sun; Video signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Intelligent Information Hiding and Multimedia Signal Processing, 2006. IIH-MSP '06. International Conference on
Conference_Location :
Pasadena, CA, USA
Print_ISBN :
0-7695-2745-0
Type :
conf
DOI :
10.1109/IIH-MSP.2006.265071
Filename :
4041791
Link To Document :
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