DocumentCode
2976743
Title
Development of tapeless lead-on-chip (LOC) packaging process with i-line photosensitive polyimide
Author
Amagai, Masazumi ; Saitoh, Tadashi ; Ohsumi, Masaki ; Kawasaki, Eui ; Yew, Chee Kiang ; Chye, Lim Thaim ; Toh, Jeffery ; Khim, Swee Yong
Author_Institution
Texas Instrum., Oita, Japan
fYear
1997
fDate
13-15 Oct 1997
Firstpage
237
Lastpage
244
Abstract
A double-sided adhesive tape is typically used as an insulator and mechanical buffer layer between the chip and lead frame in lead-on-chip (LOC) packages. The costs associated with the lead frame and tape process make the current LOC package more expensive than conventional packaging. A new tapeless LOC package process has been developed which significantly reduces the production costs. In this new process, the tape is replaced by a i-line photosensitive thermosetting polyimide layer coated on the passivation deposited wafer. This paper describes the optimum material properties for the polyimide, the fabrication process parameters, and the experimental and simulated reliability and performance results of the tapeless LOC package
Keywords
adhesion; integrated circuit manufacture; integrated circuit packaging; integrated circuit reliability; passivation; photolithography; polymer films; fabrication process parameters; i-line photosensitive polyimide; lead frame; lead-on-chip packaging process; optimum material properties; passivation deposited wafer; production costs reduction; reliability; tapeless LOC packaging process; thermosetting polyimide layer; Buffer layers; Costs; Fabrication; Insulation; Lab-on-a-chip; Material properties; Packaging; Passivation; Polyimides; Production;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 1997., Twenty-First IEEE/CPMT International
Conference_Location
Austin, TX
ISSN
1089-8190
Print_ISBN
0-7803-3929-0
Type
conf
DOI
10.1109/IEMT.1997.626924
Filename
626924
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