Effect of traps in the performance of Four Gate Transistors

In this work, a study of traps located in the bulk and the Si-SiO₂ interfaces of four gate transistors (G⁴-FETs), and their effect in the performance of these transistors, is presented. Different kinds of low frequency noise spectra measured at different voltages applied to the gates show that traps in the bulk and traps at the interfaces are the origin of such different spectra. We propose a model to evaluate low frequency noise produced in the bulk and surfaces of the device. This model is incorporated in a 2D simulator that confirms the experimental trends. It also allows us to separate the contribution of both sources and study the effects of different kinds of bulk traps on the low frequency noise.