DocumentCode :
2977615
Title :
Architectural Support for Software Transactional Memory
Author :
Saha, Bratin ; Adl-Tabatabai, Ali-Reza ; Jacobson, Quinn
fYear :
2006
fDate :
9-13 Dec. 2006
Firstpage :
185
Lastpage :
196
Abstract :
Transactional memory provides a concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. Researchers have proposed several different implementations of transactional memory, broadly classified into software transactional memory (STM) and hardware transactional memory (HTM). Both approaches have their pros and cons: STMs provide rich and flexible transactional semantics on stock processors but incur significant overheads. HTMs, on the other hand, provide high performance but implement restricted semantics or add significant hardware complexity. This paper is the first to propose architectural support for accelerating transactions executed entirely in software. We propose instruction set architecture (ISA) extensions and novel hardware mechanisms that improve STM performance. We adapt a high-performance STM algorithm supporting rich transactional semantics to our ISA extensions (called hardware accelerated software transactional memory or HASTM). HASTM accelerates fully virtualized nested transactions, supports language integration, and provides both object-based and cache-line based conflict detection. We have implemented HASTM in an accurate multi-core IA32 simulator. Our simulation results show that (1) HASTM single-thread performance is comparable to a conventional HTM implementation; (2) HASTM scaling is comparable to a STM implementation; and (3) HASTM is resilient to spurious aborts and can scale better than HTM in a multi-core setting. Thus, HASTM provides the flexibility and rich semantics of STM, while giving the performance of HTM
Keywords :
concurrency control; data structures; instruction sets; storage management; synchronisation; transaction processing; concurrency control; hardware accelerated software transactional memory; hardware transactional memory; instruction set architecture; lock-based synchronization; stock processor; transactional semantics; Acceleration; Concurrency control; Hardware; Instruction sets; Object detection; Optimizing compilers; Programming profession; Proposals; Runtime; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on
Conference_Location :
Orlando, FL
ISSN :
1072-4451
Print_ISBN :
0-7695-2732-9
Type :
conf
DOI :
10.1109/MICRO.2006.9
Filename :
4041846
Link To Document :
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