Vedic divider - A high performance computing algorithm for VLSI applications

Vedic mathematics is part of four Vedas (books of wisdom). It is part of Sthapatya Veda (book on civil engineering and architecture), an upa-veda (supplement) of Atharva Veda. It covers explanation of several modern arithmetical terms. In this paper the Parvartya yojayet algorithm is applied to develop a high performance divider and static timing analysis is done on vedic divider and conventional divider. A functionally tested 32-bit dividend and 16-bit divisor binary Vedic divider was synthesized using 32nm standard cell libraries has power saving of the order of ~109mW in comparison to conventional divider and speed of vedic divisor is ~7 times faster and area occupied is ~13 times lesser than conventional divider.