DocumentCode :
2977950
Title :
Hardware efficient architectures for coupled-form IIR filters
Author :
Yu, Fengqi ; Willson, Alan N., Jr.
Author_Institution :
Integrated Circuit & Syst. Lab., California State Univ., Los Angeles, CA, USA
Volume :
3
fYear :
1999
fDate :
36342
Firstpage :
355
Abstract :
Second-order coupled-form IIR filters have the signals in their upper and lower feedback branches coupled and processed concurrently. By use of multirate signal processing techniques, we convert this concurrent signal processing to sequential processing. Thus we obtain an interpolated coupled-form IIR filter. The hardware implementation of interpolated coupled-form IIR filters is discussed and hardware efficient architectures are proposed. We estimate the hardware complexity for a typical case with CSD (canonic signed digit) multipliers having three canonic signed digits and an input signal having a wordlength of eight bits. Without losing throughput, up to a 22% hardware reduction can be obtained for the second-order coupled form IIR filter and about 48% for the fourth-order coupled-form IIR filter
Keywords :
IIR filters; digital arithmetic; digital filters; interpolation; canonic signed digit multiplier; concurrent signal processing; coupled-form IIR filters; hardware complexity; hardware efficient architectures; hardware implementation; interpolated IIR filter; multirate signal processing techniques; second-order IIR filters; sequential processing; Clocks; Coupling circuits; Feedback; Hardware; IIR filters; Laboratories; Quantization; Signal generators; Signal processing; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-5471-0
Type :
conf
DOI :
10.1109/ISCAS.1999.778858
Filename :
778858
Link To Document :
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