DocumentCode :
2978616
Title :
ECO algorithms for removing overlaps between power rails and signal wires [IC layout]
Author :
Xiang, Hua ; Chao, Kai-Yuan ; Wong, D.F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fYear :
2002
fDate :
10-14 Nov. 2002
Firstpage :
67
Lastpage :
74
Abstract :
Design ECO (engineering change orders) commonly happens in industry due to constraints or target changes from manufacturing, marketing, reliability, or performance. At each step, designers usually want to modify the existing solution incrementally and keep the design as close as possible to the existing one. In this paper, we address the PSO (power rail - signal wire overlap) problem which solves overlaps between power rails and signal wires due to the changes in power rail design on the top layer of a multiple layer routing region. PSO problems are frequently caused by changes in power delivery system or package design. The new routing solution satisfies the following constraints: (1) Keep the routing of power rails in the new design unchanged. (2) Only the routing of the top two layers is changed. (3) Horizontal (vertical) signal wire segments on the top layer can only move up/down (left/right). (4) For each signal wire segment, the deviation (i.e., the difference between its new position and the old one) should not exceed the user-defined allowable deviation bound. For a set of industrial test circuits, we were able to remove all overlaps between power rails and signal wires with minimal wire deviation.
Keywords :
circuit CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; integrated circuit packaging; IC design ECO; PSO problems; design constraints; engineering change orders; incremental modification; manufacturing/marketing/reliability/performance target changes; multiple layer routing regions; overlap removal; package design; power delivery system design; power rail routing directions; power rail/signal wire overlap; signal wire segment position deviation bounds; top layer horizontal/vertical signal wire segments; wire deviation minimization; Circuit testing; Design engineering; Integrated circuit layout; Power engineering and energy; Rails; Railway engineering; Reliability engineering; Routing; Signal design; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
ISSN :
1092-3152
Print_ISBN :
0-7803-7607-2
Type :
conf
DOI :
10.1109/ICCAD.2002.1167515
Filename :
1167515
Link To Document :
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