Title :
On undetectable faults in partial scan circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We provide a definition of undetectable faults in partial scan circuits under a test application scheme where a test consists of primary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetectable under this test application scheme. We present experimental results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults.
Keywords :
boundary scan testing; fault simulation; finite state machines; integrated circuit design; integrated circuit testing; logic design; logic testing; at-speed primary input vectors; fault simulation; finite-state machines; partial scan circuit undetectable fault definition; scan operations; scan-per-test test application schemes; Application software; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Computational modeling; Electrical fault detection; Fault detection; Flip-flops; Sequential circuits;
Conference_Titel :
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
Print_ISBN :
0-7803-7607-2
DOI :
10.1109/ICCAD.2002.1167517
