DocumentCode
2978945
Title
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Author
Ababei, Cristinel ; Navaratnasothie, Selvakkumaran ; Bazargan, Kia ; Karypis, George
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
fYear
2002
fDate
10-14 Nov. 2002
Firstpage
181
Lastpage
185
Abstract
In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a new objective function that incorporates a truly path-based delay component for the most critical paths. To avoid semi-critical paths from becoming critical, the traditional slack-based delay component is also included in the cost function. The proposed timing driven partitioning algorithm is built on top of the hMetis algorithm, which is very efficient. Simulations results show that 14% average delay improvement can be obtained. Smooth trade-off between cutsize and delay is possible in our algorithm.
Keywords
circuit layout CAD; circuit optimisation; delay estimation; integrated circuit layout; minimisation; timing; cutsize minimization; hMetis algorithm; multi-objective circuit partitioning; multi-objective hMetis partitioning; objective function; path-based delay minimization; semi-critical paths; simultaneous minimization; slack-based delay component; timing driven partitioning algorithm; timing driven placement; Circuit simulation; Complexity theory; Cost function; Delay; Integrated circuit interconnections; Minimization; Partitioning algorithms; Time to market; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-7607-2
Type
conf
DOI
10.1109/ICCAD.2002.1167532
Filename
1167532
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