DocumentCode
2979003
Title
Sub-90 nm technologies-challenges and opportunities for CAD
Author
Karnik, Tanay ; Borkar, Shekhar ; De, Vivek
Author_Institution
Circuit Res., Intel Labs., Hillsboro, OR, USA
fYear
2002
fDate
10-14 Nov. 2002
Firstpage
203
Lastpage
206
Abstract
Future high performance microprocessor design with technology scaling beyond 90 nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practice will have to change from deterministic design to probabilistic and statistical design. This paper discusses circuit techniques and design automation opportunities to overcome the challenges.
Keywords
CMOS integrated circuits; VLSI; circuit CAD; integrated circuit design; microprocessor chips; nanoelectronics; 90 nm; CAD; CMOS scaling; EDA; circuit techniques; design automation; high performance microprocessor design; leakage power control; parameter variations; probabilistic design; statistical design; sub-90 nm technologies; technology scaling; CMOS technology; Circuits; Design automation; Energy efficiency; Frequency diversity; Logic; Microarchitecture; Microprocessors; Power generation; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-7607-2
Type
conf
DOI
10.1109/ICCAD.2002.1167535
Filename
1167535
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