Fault tolerant processor arrays based on 1½-track switch with generalized spare distributions

As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer-scale integration (WSI) is growing. The major problem for this case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. In this paper, we propose a reconfigurable processor array based on the 1½-track switch (TS) model, such that spare processing elements (PEs) are not necessarily put around the array, but are more flexibly put in the array by changing the connections of spare PEs to non-spare PEs while retaining the connections among the non-spare PEs in the same manner as those in the 1½-TS model. The proposed model has a desirable property such that the physical distances between logically adjacent PEs in the reconfigured array are within a constant, i.e. independent of the size of the array. We show that the hardware overhead of the proposed model is a little greater than that of the 1½-TS model, while the yield of the proposed model is much better than that of the 1½-TS model