Title :
Non-tree routing for reliability and yield improvement
Author :
Kahng, Andrew B. ; Liu, Bao ; Mãndoiu, Ion I.
Author_Institution :
Dept. of Comput. Sci. Eng., Univ. of California, La Jolla, CA, USA
Abstract :
We propose to introduce redundant interconnects for manufacturing yield and reliability improvement. By introducing redundant interconnects, the potential for open faults is reduced at the cost of increased potential for short faults; overall, manufacturing yield and fault tolerance can be improved. We focus on a post-processing, tree augmentation approach which can be easily integrated in current physical design flows. Experiments on randomly generated and industry testcases show that our greedy augmentation method achieves significant increase in reliability (as measured by the percentage of biconnected tree edges) with very small increase in wirelength. SPICE simulations imply that non-tree routing has smaller delay variation due to process variability.
Keywords :
SPICE; algorithm theory; circuit CAD; circuit optimisation; circuit simulation; fault tolerance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; redundancy; MRTA; Manhattan routing tree augmentation formulation; SPICE simulations; biconnected tree edges; fault tolerance; greedy algorithms; greedy augmentation methods; manufacturing yield improvement; nontree routing; open fault reduction; post-processing tree augmentation; post-routing optimization; process variability delay variation; redundant interconnects; reliability improvement; short faults; wirelength; Circuit faults; Costs; Delay; Integrated circuit interconnections; Manufacturing; Packaging; Redundancy; Routing; Runtime; SPICE;
Conference_Titel :
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
Print_ISBN :
0-7803-7607-2
DOI :
10.1109/ICCAD.2002.1167544