An expert system for incorporating design for testability in programmable logic arrays

The task of designing reliable very large-scale integrated (VLSI) chips is difficult, due to the small device geometries. This situation forces the designers to incorporate testability as part of design. Numerous techniques for incorporating testability in programmable logic arrays have been evolved. The selection of a testability technique which is viable for a particular design requires much decision making. Thus there is a potential of effectively utilizing the decision-making capabilities of an expert system in this domain. Here, an expert system which selects a testability technique for a given design and generates a modified version is presented