A VLSI architecture for cellular automata based Reed-Solomon decoder

The design of cellular automata (CA)-based SbEC-DbED (single-byte error correcting, double-byte error detecting) code, which is analogous to the extended Reed-Solomon (RS) code, was proposed by D.R. Chowdhury et al. (1994). This code has the same restriction on error correction capability as that of the extended RS code. In this paper, a new scheme has been proposed for pipeline implementation of CA-based tbEC-tbED (t-byte error correcting, t-byte error detecting) codes that are analogous to the conventional RS code. The encoder and decoder of this code can both be implemented in a pipeline with a CA array. The proposed decoder provides a simple, modular and cost-effective design that is ideally suited for VLSI implementation