New cellular array for the hardware implementation of very high speed digital filter

A new pipeline sequential processor system is proposed. The system takes the form of a cellular array the basic element of which is a sequential synchronous full adder. The proposed system is used to build a very high speed digital filter. The execution time of any term A_i .X_i (i=0, 1, …, N) of the digital filter equation is the time of three clock cycles. The time is constant and completely independent on the word length. The basic element of the proposed array consists of two flip-flops. The analysis of the logic capabilities of the flip-flop showed that it is possible to implement any of the sixteen possible functions of two variables directly in the flip-flop. The next state of the flip-flop represents the result of the logic function. The two flip-flops of the basic element are used to realise the function of the single-bit full adder, one to form the sum S and the other to form the carry C_i, where: S=X⊕Y⊕C_i-1, and C_i=X.Y+(X¯+Y¯).C_i-1 The complete hardware of the basic element, the cellular array and that of the digital filter are given. The new cellular array results in great saving in the computation time compared with the conventional techniques. A comparison is given between this new hardware and the conventional ones based on the time-hardware product as a criterion. The comparison proved that the new hardware reduces the time-hardware product