Title :
Circuit simulation of CMOS faults
Author :
Koe, Wern-Yan ; Midkiff, Scott F.
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
The effect of short and open faults in CMOS circuits across a wide range of resistances using circuit, rather than logic, simulation is investigated. Circuit simulation is used to predict the rising and falling propagation delays and the supply current consumption for faulty and fault-free circuits when test vectors are applied. These results indicate the suitability of proposed fault detection techniques. Results for short and open faults in an inverter chain and in a complex gate full-adder are reported
Keywords :
CMOS integrated circuits; adders; circuit analysis computing; invertors; CMOS faults; circuit simulation; fault detection techniques; fault-free circuits; full-adder; inverter chain; open faults; propagation delays; short faults; supply current consumption; test vectors; CMOS digital integrated circuits; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Current supplies; Electrical fault detection; Fault detection; Propagation delay; Semiconductor device modeling;
Conference_Titel :
Southeastcon '88., IEEE Conference Proceedings
Conference_Location :
Knoxville, TN
DOI :
10.1109/SECON.1988.194821
