Title :
Whirlpool PLAs: a regular logic structure and their synthesis
Author :
Mo, Fan ; Brayton, Robert K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is logically a four-level Boolean NOR network. By arranging the four logic arrays in a cycle, a compact layout is achieved. Doppio-ESPRESSO, a four-level logic minimization algorithm is developed for WPLA synthesis. No technology mapping, placement or routing is necessary for the WPLA. Area and delay trade-off is absent, because these two goals are usually compatible in WPLA synthesis.
Keywords :
Boolean functions; combinational circuits; finite state machines; logic CAD; minimisation of switching nets; multivalued logic circuits; programmable logic arrays; WPLA; Whirlpool PLAs; combinational logic; compact layout; finite state machines; four-level Boolean NOR network; four-level logic minimization algorithm; logic arrays; regular logic structure; Boolean functions; Circuit synthesis; Delay; Integrated circuit interconnections; Iris; Logic arrays; Minimization methods; Programmable logic arrays; Routing; Timing;
Conference_Titel :
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
Print_ISBN :
0-7803-7607-2
DOI :
10.1109/ICCAD.2002.1167585
