DocumentCode
2980056
Title
Modeling the Drain Current of DG FD SOI NMOS Devices with N+/P+ Poly Top/Bottom Gate
Author
Hsu, C.H. ; Kuo, J.B.
Author_Institution
Nat. Taiwan Univ., Taipei
fYear
2007
fDate
20-22 Dec. 2007
Firstpage
59
Lastpage
62
Abstract
This paper reports an analytical drain current model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n+/p+ poly top/ bottom gate considering the threshold/ transition voltage effects. Via a comprehensive current conduction mechanism model, the analytical drain current model considering the threshold/transition voltage effects could provide an accurate prediction of performance the 100 nm DG FD SOI NMOS device with the n+/p+ poly top/bottom gate as verified by the 2D simulation results.
Keywords
MOS integrated circuits; silicon-on-insulator; 2D simulation; analytical drain current model; comprehensive current conduction mechanism model; double-gate fully-depleted SOI NMOS devices; poly top-bottom gate; threshold-transition voltage effects; Analytical models; CMOS technology; Electrons; Hydrogen; MOS devices; Nanoscale devices; Performance analysis; Predictive models; Threshold voltage; Video recording;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location
Tainan
Print_ISBN
978-1-4244-0637-1
Electronic_ISBN
978-1-4244-0637-1
Type
conf
DOI
10.1109/EDSSC.2007.4450061
Filename
4450061
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