Title :
Multilevel gold metallization
Author :
Haberle, K. ; Langheinrich, W. ; Dudek, V. ; Hefner, H.-A. ; Isernhagen, R.
Author_Institution :
Inst. of Semicond. Electron., Tech. Univ. of Darmstadt, West Germany
Abstract :
A process sequence for multilevel gold metallization of VLSI circuits has been developed. In this process, polyimide is used as an isolation layer. In order to minimize problems with planarization, the interconnections between metallization layers are made by gold pillars with completely fill the via holes. Plane conductor metallization levels are the results. The double-layer gold metallization process is presented, and the critical steps are discussed in detail.<>
Keywords :
VLSI; gold; integrated circuit technology; metallisation; Au pillars; VLSI circuits; multilevel Au metallisation; planarization; plane conductor metallisation levels; polyimide isolation layer; process sequence; via hole filling; Cathodes; Conducting materials; Fabrication; Gold; Integrated circuit interconnections; Metallization; Nonhomogeneous media; Polyimides; Very large scale integration; Wiring;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1988. Proceedings., Fifth International IEEE
Conference_Location :
Santa Clara, CA, USA
DOI :
10.1109/VMIC.1988.14183
