Dimensional Effects of Fast and Slow Interface Trap Generation on Flash Memory Cells

In this paper, interface trap generation rate dependence on large and small active area dimensions is clearly characterized. Both in D.C. (FN-CCS) and A.C. (program/erase cycling) test conditions, we have discovered that the role of interface trap has predominated the whole oxide degradation process over oxide-trapped charge as the channel width decreases to sub-100 nm dimensions. Through different tunnel oxide thickness and channel concentrations, slow interface trap (or border trap) has firstly and statistically been characterized by the method of Direct-Current Current-Voltage (DCIV) technique. We also Abstract-In this paper, interface trap generation rate dependence on large and small active area dimensions is clearly characterized. Both in D.C. (FN-CCS) and A.C. (program/erase cycling) test conditions, we have discovered that the role of interface trap has predominated the whole oxide degradation process over oxide-trapped charge as the channel width decreases to sub-100 nm dimensions. Through different tunnel oxide thickness and channel concentrations, slow interface trap (or border trap) has firstly and statistically been characterized by the method of Direct-Current Current-Voltage (DCIV) technique. We also present the possible root cause to explain the phenomenon of channel concentration dependent reliability performance. One is the issue of tunneling current uniformity; the other is that of the secondary hot hole generation probability, which is relevant to Auger recombination and generation processes.present the possible root cause to explain the phenomenon of channel concentration dependent reliability performance. One is the issue of tunneling current uniformity; the other is that of the secondary hot hole generation probability, which is relevant to Auger recombination and generation processes.