A new mapping technique for automated design of highly efficient multiplexed FIR digital filters

In the face of a permanently increasing generic throughput rate of digital CMOS circuits in combination with constant throughput requirements for a variety of applications, strategies for time-sharing become more and more important. Thus, this paper presents a systematic mapping approach leading to efficient VLSI-architectures for applications with a wide range of system parameters. Due to the regularity and scalability of the resulting architectures, optimized CMOS macros for different system requirements can be automatically tiled using only a small set of basic cells. Therefore the design effort is kept small. In the first step of the approach the folding technique is applied at bit-level. The free parameters of this technique are then fixed in a second step according to guidelines which are derived from design-strategies for efficient VLSI-architectures. In order to demonstrate the efficiency and the flexibility of this approach new classes of efficient time-shared FIR-filters will be derived that cover applications like adaptive equalizers as well as matched filters for rapid code acquisition in spread spectrum receivers. Realized filter macros show the very small silicon area achievable with the presented mapping technique