A design and tool reuse methodology for rapid prototyping of application specific instruction set processors

Author

Kim, Young Geol ; Kim, Tag Gon

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

fYear

1999

fDate

36342

Firstpage

46

Lastpage

51

Abstract

This paper proposes a design method and a tool reuse scheme for the rapid prototyping of application-specific instruction-set processors (ASIPs). We propose a three-level hierarchical architecture abstraction method for top-down processor design. We also propose a reusable architecture description language (READ) and a family of retargetable simulators that allow top-down processor description and prototyping from instruction-set design to RTL implementation

Keywords

application specific integrated circuits; instruction sets; logic CAD; microprocessor chips; reconfigurable architectures; READ language; RTL implementation; application-specific instruction-set processors; design methodology; hierarchical architecture abstraction method; instruction-set design; rapid prototyping; register transfer level; retargetable simulators; reusable architecture description language; tool reuse scheme; top-down processor description; top-down processor design; Decision support systems; Prototypes; Virtual reality;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid System Prototyping, 1999. IEEE International Workshop on

Conference_Location

Clearwater, FL

Print_ISBN

0-7695-0246-6

Type

conf

DOI

10.1109/IWRSP.1999.779030

Filename

779030