ATM traffic management systems: ASIC fast prototyping

Presents an industrial prototype of an ATM telecommunications traffic management system as an application of a methodology for the rapid prototyping of ASIC-based systems on FPGAs. A study of different systems requiring buffer management and cell scheduling functions to support an integrated management of the ATM traffic classes makes it possible to identify a core of high-level functions that is common to all the analysed systems. These primitives have to be combined with some application-specific functions and interfaces in order to meet the requirements of each system, thus enhancing the flexibility of the design and allowing time savings in the development, simulation and test phases. Each hardware function is implemented by combining one or more VHDL macrocells, following a methodology that enhances testability and reusability. As an example, we present one of the possible systems that has been prototyped by a board equipped with a microprocessor, a set of FPGAs and the necessary commercial components. An experimental test is performed by inserting the board in a real environment with the purpose of validating the implementation of the algorithms, evaluating their efficiency under real-time traffic conditions, and setting the values of some critical parameters