Optimal design of a Half Wave Cockroft-Walton Voltage Multiplier with different capacitances per stage

Even though the half-wave Cockroft-Walton voltage multiplier (H-W C-W VM) is one of the most common AC-DC step-up topologies, most of the VM designers persist in using equal capacitances in every stage, a fact that leads to a non optimal design. The aim of this paper is to introduce a new designing method of H-W C-W VM that lays both on the choice of the adequate capacitance values to minimize the output voltage drop and ripple and the calculation of the optimal number of stages that is necessary to produce the desired output voltage with the minimum base capacitance value. In this way the voltage gain is maximized and the required capacitance value per stage is minimized. The theoretical analysis is validated by PSPICE simulations and experimental results, accomplished on laboratory prototypes.