FPGA partitioning for rapid prototyping: a 1 million gate design case study

This paper discusses the FPGA partitioning strategies for open rapid prototyping boards and proprietary prototyping systems, where the constraints of a low number of utilized devices and high performance are critical. Partitioning should handle large designs and produce efficient solutions. The paper first presents the advanced partitioning strategies and then considers a case study example of 1 million gates. The required partitioning solution was obtained by combining the described manual and automatic partitioning and pin multiplexing techniques