Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin /spl times/16 DDR SDRAM

Author

Jung-Bae Lee ; Kyu-Hyoun Kim ; Changsik Yoo ; Sangbo Lee ; One-Gyun Na ; Chan-Yong Lee ; Ho-Young Song ; Jong-Soo Lee ; Zi-Hyoun Lee ; Ki-Woong Yeom ; Hoi-Joo Chung ; Il-Won Seo ; Moo-Sung Chae ; Yun-Ho Choi ; Soo-In Cho

Author_Institution

Samsung Electron., Samsung Electron., Kyunggi-Do, South Korea

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

68

Lastpage

69

Abstract

DLL and improved I/O circuits are for 500 Mb/s/pin DDR SDRAM. This digitally-controlled DLL has inherent duty cycle correction capability, enabling fast re-locking upon standby-mode exit. Data input circuits, such as internal delay control and digital sense amplifier, reduce setup/hold window to 0.3 ns. The output data driver has 62% decreased pattern-dependent skew.

Keywords

DRAM chips; delay lock loops; digital control; 500 Mbit/s; DDR SDRAM; DLL circuit; I/O circuit; data input circuit; data setup/hold time; digital control; digital sense amplifier; duty cycle correction; internal delay control; output data driver; skew; Added delay; Circuits; Clocks; DRAM chips; Delay effects; Latches; Phase detection; Random access memory; Uncertainty; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912550

Filename

912550