Title :
Circuit design for a 2.2 GB/s memory interface
Author :
Sidiropoulos, S. ; Abhyankar, A. ; Chen, C. ; Chang, K. ; Tsu-Ju Chin ; Hays, N. ; Jun Kim ; Ying Li ; Tsang, G. ; Wong, A. ; Stark, D.
Author_Institution :
Rambus Inc., Mountain View, CA, USA
Abstract :
A 2.2 GB/s signaling interface for main memory uses a DLL that allows for in-system timing calibration with 1.4/spl deg/ resolution, and output drivers with limited positive feedback to increase voltage margin. In a 0.25 /spl mu/m CMOS process, the prototype chips operate to 2.6 GB/s.
Keywords :
CMOS memory circuits; calibration; circuit feedback; delay lock loops; driver circuits; timing; 0.25 micron; 2.2 GB/s; CMOS chip; DLL; memory circuit; output driver; positive feedback; signaling interface; timing calibration; voltage margin; Bandwidth; Circuit synthesis; Clocks; Delay; Driver circuits; Frequency; Random access memory; Registers; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912551
